This relates generally to integrated circuits, and more particularly, to integrated circuits with decoupling capacitors.
Decoupling capacitors are often used to help provide more stable power supply voltages to circuitry on an integrated circuit. Decoupling capacitors shunt high frequency noise on direct current (DC) power supply lines to ground power supply lines, thereby preventing the noise from reaching circuit components on the integrated circuit. In a scenario in which a power supply is required to switch between different modes of operation, an adequate decoupling capacitance can act as an energy reserve that lessens the magnitude of undesired dips in power supply voltage during mode switching events.
Advances in integrated circuit design require power supplies to supply stable power for integrated circuits operating at high data rates and clock speeds. This requires increasing amounts of decoupling capacitance per unit integrated circuit area. A large decoupling capacitance could occupy a disproportionate amount of valuable surface area on an integrated circuit.
A convention decoupling capacitor (commonly referred to as a planar decoupling capacitor) includes two doped oxide definition (OD) regions formed in a semiconductor substrate. The two OD regions are separated by an intervening region (i.e., a region that is part of the substrate). A single continuous layer of conductive gate material is disposed over the intervening region. A layer of dielectric material (i.e., silicon dioxide) is interposed between the surface of the intervening region in the substrate and the layer of conductive gate material. The layer of conductive gate material serves as a first conductive plate for the decoupling capacitor, whereas the surface of the intervening region that faces the conductive gate material serves as a second conductive plate for the decoupling capacitor. Integrated circuits that include such types of decoupling capacitors may have a significant portion of available die space occupied by decoupling capacitor circuitry.
Strict polysilicon density requirements in modern fabrication processes, however, do not permit the formation of decoupling capacitors that have large continuous layers of conductive gate material (i.e., capacitive structures need to be split into more than two oxide definition regions having multiple thinner conductive gate structures connected in parallel). Forming planar decoupling capacitors with split OD regions and multiple parallel-connected gate structures may undesirably decrease the capacitance per unit area of the decoupling capacitors.